Terminating F100K ECL Inputs Introduction
cuit. The designer should be aware that although Figure2A, Figure 2B, and Figure 2C supply ECL compatible sig-
ing F100K ECL
Many F100K designs require that certain inputs be pre-
nals levels, they differ in power consumption and suscepti-
sented with a HIGH or LOW level. Because of the con-
bility to changes in temperature and VEE.
struction of the F100K input circuitry, a LOW can berealized by simply leaving the input OPEN. However, a
For designs where there are multiple unused inputs and
HIGH must be terminated in a special way. Simply tying the
extra logic gates available, fanout from the unused gates is
possible. As an example, one gate of the 100302 is capa-
ble of driving ten quiescent inputs at voltage and currentlevels typical of F100K as shown in Figure 3. Design Considerations
Figure 4 shows in detail the F100K pull-up scheme and the
IH and VIL across VEE (−4.2V to −5.7V for
input circuitry. Although the circuits of Figure 2 are good
F100K ECL 300 Series) are −870 mV to −1165 mV and
examples, a detailed circuit analysis must include the
−1475 mV to −1830 mV respectively. By staying within
50 kΩ input resistor. In Figure 4A, the resistor (RD) which
these ranges, proper input conditions are assured. Figure 1
sets the diode biasing current is in parallel with the 50 kΩ
shows the voltage versus current for the F100K input tran-
input resistor. Similarly, the circuit of Figure 4B shows that
sistor. If the input is tied to VCC/VCCA the input transistor
R2 is in parallel with the input resistor.
saturates (Point D) which can damage internal circuitry.
The point to emphasize is never tie an F100K input to VCC/
The best VIH to realize a HIGH is a voltage drop of 0.9V
VCCA in order to realize a HIGH preset. Instead, the follow-
below VCC/VCCA. As can be seen from the graph, this
locates the quiescent point on the flat part of the curve
• For a LOW level — leave input open or tie to V
(Point C) midway within the acceptable range of V
ure 2 shows three ways in which a HIGH can be realized
• For a HIGH level — tie input to a diode drop or 0.9V
on the input. These circuits allow the user to maintain con-
stant input signals at optimum levels of VEE and tempera-
Remember also that the 50 kΩ input resistor must be con-
ture. Each circuit can handle multiple fanouts, the number
sidered in the circuit parameter calculations.
will depend upon the maximum current capability of the cir-
A = 50 KΩ Pull-Down CurrentB = Transition (Switching) RegionC = Base Current plus 50 kΩD = Input Transistor Saturation
FIGURE 1. Input Characteristics
2001 Fairchild Semiconductor Corporation
Design Considerations (Continued) Note: Nominal values are shown. FIGURE 2. Equivalent Circuits for HIGH Termination FIGURE 3. Utilizing Unused Gates to Terminate Multiple HIGHs and LOWs Design Conside gn Conside ations e rm in at ing F100K ECL FIGURE 4. Pull-Up Circuit Examples
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY
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Terminating F100K ECL Inputs
Design Considerations (Continued)
Design Conside